GitLab

Add optional regular expression to AUTOINOUTMODULE.
(verilog-inject-auto, verilog-auto-arg, verilog-auto-inst)
(verilog-auto-inst-param, verilog-auto-reg)
(verilog-auto-reg-input, verilog-auto-wire, verilog-auto-output)
(verilog-auto-output-every, verilog-auto-input)
(verilog-auto-inout, verilog-auto-sense, verilog-auto-tieoff)
(verilog-auto-unused, verilog-auto): Update documentation to use
more obvious instance module names versus cell names.