Commit 0d60bfc4 authored by Friedrich Beckmann's avatar Friedrich Beckmann Committed by Lars Ingebrigtsen

Fix ModelSim error parsing

* lisp/progmodes/vhdl-mode.el (vhdl-compiler-alist): Fix
ModelSim error parsing (bug#5768).

Copyright-paperwork-exempt: yes
parent 5cac11aa
......@@ -266,9 +266,14 @@ Overrides local variable `indent-tabs-mode'."
;; WARNING[2]: test.vhd(85): Possible infinite loop
;; ** Warning: [4] ../src/emacsvsim.vhd(43): An abstract ...
;; ** Error: adder.vhd(190): Unknown identifier: ctl_numb
;; ** Error: counter_rtl.vhd(18): Nonresolved signal 'hallo' has multiple sources.
;; Drivers:
;; counter_rtl.vhd(27):Conditional signal assignment line__27
;; counter_rtl.vhd(29):Conditional signal assignment line__29
("ModelSim" "vcom" "-93 -work \\1" "make" "-f \\1"
nil "vlib \\1; vmap \\2 \\1" "./" "work/" "Makefile" "modelsim"
("^\\(ERROR\\|WARNING\\|\\*\\* Error\\|\\*\\* Warning\\)[^:]*:\\( *\\[[0-9]+]\\)? \\([^ \t\n]+\\)(\\([0-9]+\\)):" 3 4 nil) ("" 0)
("\\(ERROR:\\|WARNING\\[[0-9]+\\]:\\|\\*\\* Error:\\|\\*\\* Warning: \\[[0-9]+\\]\\| +\\) \\([^ ]+\\)(\\([0-9]+\\)):" 2 3 nil)
("" 0)
("\\1/_primary.dat" "\\2/\\1.dat" "\\1/_primary.dat"
"\\1/_primary.dat" "\\1/body.dat" downcase))
;; ProVHDL, Synopsys LEDA: provhdl -w work -f test.vhd
......
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