Commit 47086495 authored by Wilson Snyder's avatar Wilson Snyder Committed by Stefan Monnier

Merge verilog-mode.el from upstream.

* progmodes/verilog-mode.el (font-lock-keywords):
Fix mis-highligting auto.  Reported by Craig Barner.
(verilog-auto, verilog-auto-undef): Add AUTOUNDEF to remove
defines from global name space. Reported by Dan Dever.
(verilog-auto-reset, verilog-auto-reset-widths)
(verilog-auto-tieoff): Support using unbased numbers for
AUTORESET and AUTOTIEOFF.
(verilog-submit-bug-report): Update variable list.
(verilog-read-auto-params): Fix AUTOINPUT regexps containing
parenthesis from not matching. Reported by Michael Rytting.
(verilog-auto-template-lint): Fix hash error when linting modules
with no used templates.
(verilog-warn, verilog-warn-error)
(verilog-warn-fatal): When non-interactive report multiple
warnings before exiting.  Suggested by Brad Dobbie.
(verilog-auto-template-lint, verilog-auto-template-warn-unused)
(verilog-read-auto-template): Add `verilog-auto-template-warn-unused'
to report unused template errors.  Reported by Brad Dobbie.
(verilog-read-decls): Fix AUTOWIRE etc on supply0, supply1 type
nets, bug438. Reported by Vns Blore.
(verilog-auto-inout-module, verilog-auto-reg)
(verilog-read-decls, verilog-read-sub-decls-sig)
(verilog-signals-edit-wire-reg, verilog-signals-with):
Fix passing of Verilog data types in ANSI input/output ports
such as "output logic" into the AUTOs. Special case "wire" and
"reg" for backwards compatibility presuming Verilog 2001.
(verilog-auto-ascii-enum): Add "auto enum" as alias.
(verilog-preprocess): Fix replication of preprocess output.
Reported by Brad Dobbie.
(verilog-auto-inst-interfaced-ports):
Create verilog-auto-inst-interfaced-ports, bug429.
Reported by Julian Gorfajn.
(verilog-after-save-font-hook)
(verilog-before-save-font-hook): New variable.
(verilog-modi-cache-results, verilog-save-font-mod-hooked)
(verilog-save-font-mods): Wrap disabling fontification, reported
by David Rogoff.
(verilog-do-indent, verilog-pretty-declarations-auto)
(verilog-sk-def-reg): Fix obeying `verilog-auto-lineup', bug305.
Reported by Pierre-David Pfister.
(verilog-set-auto-endcomments): Fix endtask auto comments outside
of class declarations, bug292.  Reported by Kevin Heilman.
(verilog-read-decls): Fix 'parameter type' not appearing in
AUTOINSTPARAM, bug340.  Reported by Jonathan Greenlaw.
(verilog-auto-logic): Fix when AUTOLOGIC present to properly do
AUTOINPUTs, bug411. Reported by Jonathan Greenlaw.
(verilog-read-auto-lisp): Avoid syntax-ppss warning on AUTOLISP.
Reported by David Kravitz.

* progmodes/verilog-mode.el (verilog-pretty-expr): Don't line up
assignment with tests in ifs and for loops.
(verilog-extended-complete-re, verilog-complete-reg): Change so
that DPI inport functions don't look like fuction declarations.
(verilog-pretty-expr): Don't line up assignment
operations to the test and increment in if and for loops
(verilog-extended-complete-re, verilog-complete-reg): Change so
that DPI inport functions don't look like fuction declarations
parent c7349e19
2012-05-03 Wilson Snyder <wsnyder@wsnyder.org>
* progmodes/verilog-mode.el (font-lock-keywords):
Fix mis-highligting auto. Reported by Craig Barner.
(verilog-auto, verilog-auto-undef): Add AUTOUNDEF to remove
defines from global name space. Reported by Dan Dever.
(verilog-auto-reset, verilog-auto-reset-widths)
(verilog-auto-tieoff): Support using unbased numbers for
AUTORESET and AUTOTIEOFF.
(verilog-submit-bug-report): Update variable list.
(verilog-read-auto-params): Fix AUTOINPUT regexps containing
parenthesis from not matching. Reported by Michael Rytting.
(verilog-auto-template-lint): Fix hash error when linting modules
with no used templates.
(verilog-warn, verilog-warn-error)
(verilog-warn-fatal): When non-interactive report multiple
warnings before exiting. Suggested by Brad Dobbie.
(verilog-auto-template-lint, verilog-auto-template-warn-unused)
(verilog-read-auto-template): Add `verilog-auto-template-warn-unused'
to report unused template errors. Reported by Brad Dobbie.
(verilog-read-decls): Fix AUTOWIRE etc on supply0, supply1 type
nets, bug438. Reported by Vns Blore.
(verilog-auto-inout-module, verilog-auto-reg)
(verilog-read-decls, verilog-read-sub-decls-sig)
(verilog-signals-edit-wire-reg, verilog-signals-with):
Fix passing of Verilog data types in ANSI input/output ports
such as "output logic" into the AUTOs. Special case "wire" and
"reg" for backwards compatibility presuming Verilog 2001.
(verilog-auto-ascii-enum): Add "auto enum" as alias.
(verilog-preprocess): Fix replication of preprocess output.
Reported by Brad Dobbie.
(verilog-auto-inst-interfaced-ports):
Create verilog-auto-inst-interfaced-ports, bug429.
Reported by Julian Gorfajn.
(verilog-after-save-font-hook)
(verilog-before-save-font-hook): New variable.
(verilog-modi-cache-results, verilog-save-font-mod-hooked)
(verilog-save-font-mods): Wrap disabling fontification, reported
by David Rogoff.
(verilog-do-indent, verilog-pretty-declarations-auto)
(verilog-sk-def-reg): Fix obeying `verilog-auto-lineup', bug305.
Reported by Pierre-David Pfister.
(verilog-set-auto-endcomments): Fix endtask auto comments outside
of class declarations, bug292. Reported by Kevin Heilman.
(verilog-read-decls): Fix 'parameter type' not appearing in
AUTOINSTPARAM, bug340. Reported by Jonathan Greenlaw.
(verilog-auto-logic): Fix when AUTOLOGIC present to properly do
AUTOINPUTs, bug411. Reported by Jonathan Greenlaw.
(verilog-read-auto-lisp): Avoid syntax-ppss warning on AUTOLISP.
Reported by David Kravitz.
2012-05-03 Michael McNamara <mac@mail.brushroad.com>
* progmodes/verilog-mode.el (verilog-pretty-expr): Don't line up
assignment with tests in ifs and for loops.
(verilog-extended-complete-re, verilog-complete-reg): Change so
that DPI inport functions don't look like fuction declarations.
(verilog-pretty-expr): Don't line up assignment
operations to the test and increment in if and for loops
(verilog-extended-complete-re, verilog-complete-reg): Change so
that DPI inport functions don't look like fuction declarations
2012-05-03 Kenichi Handa <handa@m17n.org>
* mail/rmailmm.el (rmail-show-mime): Catch an error caused by text
......
......@@ -123,9 +123,9 @@
;;; Code:
;; This variable will always hold the version number of the mode
(defconst verilog-mode-version "725"
(defconst verilog-mode-version "800"
"Version of this Verilog mode.")
(defconst verilog-mode-release-date "2011-11-27-GNU"
(defconst verilog-mode-release-date "2012-04-23-GNU"
"Release date of this Verilog mode.")
(defconst verilog-mode-release-emacs t
"If non-nil, this version of Verilog mode was released with Emacs itself.")
......@@ -415,7 +415,10 @@ Set `verilog-in-hooks' during this time, to assist AUTO caches."
:group 'verilog-mode)
(defvar verilog-debug nil
"If set, enable debug messages for `verilog-mode' internals.")
"Non-nil means enable debug messages for `verilog-mode' internals.")
(defvar verilog-warn-fatal nil
"Non-nil means `verilog-warn-error' warnings are fatal `error's.")
(defcustom verilog-linter
"echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'"
......@@ -524,6 +527,8 @@ are lineup only when \\[verilog-pretty-declarations] is typed."
(const :tag "Line up Declarations" declarations)
(function :tag "Other"))
:group 'verilog-mode-indent )
(put 'verilog-auto-lineup 'safe-local-variable
'(lambda (x) (memq x '(nil all assignments declarations))))
(defcustom verilog-indent-level 3
"Indentation of Verilog statements with respect to containing block."
......@@ -600,40 +605,39 @@ Set to 0 to have all directives start at the left side of the screen."
(put 'verilog-case-indent 'safe-local-variable 'integerp)
(defcustom verilog-auto-newline t
"True means automatically newline after semicolons."
"Non-nil means automatically newline after semicolons."
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-auto-newline 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-indent-on-newline t
"True means automatically indent line after newline."
"Non-nil means automatically indent line after newline."
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-auto-indent-on-newline 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-tab-always-indent t
"True means TAB should always re-indent the current line.
"Non-nil means TAB should always re-indent the current line.
A nil value means TAB will only reindent when at the beginning of the line."
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-tab-always-indent 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-tab-to-comment nil
"True means TAB moves to the right hand column in preparation for a comment."
"Non-nil means TAB moves to the right hand column in preparation for a comment."
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-tab-to-comment 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-indent-begin-after-if t
"If true, indent begin statements following if, else, while, for and repeat.
"Non-nil means indent begin statements following if, else, while, etc.
Otherwise, line them up."
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-indent-begin-after-if 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-align-ifelse nil
"If true, align `else' under matching `if'.
"Non-nil means align `else' under matching `if'.
Otherwise else is lined up with first character on line holding matching if."
:group 'verilog-mode-indent
:type 'boolean)
......@@ -648,7 +652,7 @@ default avoids too many redundant comments in tight quarters."
(put 'verilog-minimum-comment-distance 'safe-local-variable 'integerp)
(defcustom verilog-highlight-p1800-keywords nil
"True means highlight words newly reserved by IEEE-1800.
"Non-nil means highlight words newly reserved by IEEE-1800.
These will appear in `verilog-font-lock-p1800-face' in order to gently
suggest changing where these words are used as variables to something else.
A nil value means highlight these words as appropriate for the SystemVerilog
......@@ -659,7 +663,7 @@ to see the effect as font color choices are cached by Emacs."
(put 'verilog-highlight-p1800-keywords 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-highlight-grouping-keywords nil
"True means highlight grouping keywords 'begin' and 'end' more dramatically.
"Non-nil means highlight grouping keywords 'begin' and 'end' more dramatically.
If false, these words are in the `font-lock-type-face'; if True then they are in
`verilog-font-lock-ams-face'. Some find that special highlighting on these
grouping constructs allow the structure of the code to be understood at a glance."
......@@ -668,7 +672,7 @@ grouping constructs allow the structure of the code to be understood at a glance
(put 'verilog-highlight-grouping-keywords 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-highlight-modules nil
"True means highlight module statements for `verilog-load-file-at-point'.
"Non-nil means highlight module statements for `verilog-load-file-at-point'.
When true, mousing over module names will allow jumping to the
module definition. If false, this is not supported. Setting
this is experimental, and may lead to bad performance."
......@@ -677,7 +681,7 @@ this is experimental, and may lead to bad performance."
(put 'verilog-highlight-modules 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-highlight-includes t
"True means highlight module statements for `verilog-load-file-at-point'.
"Non-nil means highlight module statements for `verilog-load-file-at-point'.
When true, mousing over include file names will allow jumping to the
file referenced. If false, this is not supported."
:group 'verilog-mode-indent
......@@ -689,7 +693,7 @@ file referenced. If false, this is not supported."
Set this to \"wire\" if the Verilog code uses \"`default_nettype
none\". Note using `default_nettype none isn't recommended practice; this
mode is experimental."
:version "24.1"
:version "24.1" ;; rev670
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-auto-declare-nettype 'safe-local-variable `stringp)
......@@ -697,27 +701,27 @@ mode is experimental."
(defcustom verilog-auto-wire-type nil
"Non-nil specifies the data type to use with `verilog-auto-wire' etc.
Set this to \"logic\" for SystemVerilog code, or use `verilog-auto-logic'."
:version "24.1"
:version "24.1" ;; rev673
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-auto-wire-type 'safe-local-variable `stringp)
(defcustom verilog-auto-endcomments t
"True means insert a comment /* ... */ after 'end's.
"Non-nil means insert a comment /* ... */ after 'end's.
The name of the function or case will be set between the braces."
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-auto-endcomments 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-delete-trailing-whitespace nil
"True means to `delete-trailing-whitespace' in `verilog-auto'."
:version "24.1"
"Non-nil means to `delete-trailing-whitespace' in `verilog-auto'."
:version "24.1" ;; rev703
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-auto-delete-trailing-whitespace 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-ignore-concat nil
"True means ignore signals in {...} concatenations for AUTOWIRE etc.
"Non-nil means ignore signals in {...} concatenations for AUTOWIRE etc.
This will exclude signals referenced as pin connections in {...}
from AUTOWIRE, AUTOOUTPUT and friends. This flag should be set
for backward compatibility only and not set in new designs; it
......@@ -727,7 +731,7 @@ may be removed in future versions."
(put 'verilog-auto-ignore-concat 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-read-includes nil
"True means to automatically read includes before AUTOs.
"Non-nil means to automatically read includes before AUTOs.
This will do a `verilog-read-defines' and `verilog-read-includes' before
each AUTO expansion. This makes it easier to embed defines and includes,
but can result in very slow reading times if there are many or large
......@@ -750,15 +754,15 @@ sub-module's port list has changed."
:type '(choice (const nil) (const ask) (const detect) (const force)))
(defcustom verilog-auto-star-expand t
"Non-nil indicates to expand a SystemVerilog .* instance ports.
They will be expanded in the same way as if there was a AUTOINST in the
"Non-nil means to expand SystemVerilog .* instance ports.
They will be expanded in the same way as if there was an AUTOINST in the
instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'."
:group 'verilog-mode-actions
:type 'boolean)
(put 'verilog-auto-star-expand 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-star-save nil
"Non-nil indicates to save to disk SystemVerilog .* instance expansions.
"Non-nil means save to disk SystemVerilog .* instance expansions.
A nil value indicates direct connections will be removed before saving.
Only meaningful to those created due to `verilog-auto-star-expand' being set.
......@@ -964,7 +968,7 @@ you will probably also need `verilog-auto-reset-widths' set."
(put 'verilog-active-low-regexp 'safe-local-variable 'stringp)
(defcustom verilog-auto-sense-include-inputs nil
"If true, AUTOSENSE should include all inputs.
"Non-nil means AUTOSENSE should include all inputs.
If nil, only inputs that are NOT output signals in the same block are
included."
:group 'verilog-mode-auto
......@@ -972,7 +976,7 @@ included."
(put 'verilog-auto-sense-include-inputs 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-sense-defines-constant nil
"If true, AUTOSENSE should assume all defines represent constants.
"Non-nil means AUTOSENSE should assume all defines represent constants.
When true, the defines will not be included in sensitivity lists. To
maintain compatibility with other sites, this should be set at the bottom
of each Verilog file that requires it, rather than being set globally."
......@@ -981,28 +985,36 @@ of each Verilog file that requires it, rather than being set globally."
(put 'verilog-auto-sense-defines-constant 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-reset-blocking-in-non t
"If true, AUTORESET will reset those signals which were
assigned with blocking assignments (=) even in a block with
non-blocking assignments (<=).
"Non-nil means AUTORESET will reset blocking statements.
When true, AUTORESET will reset in blocking statements those
signals which were assigned with blocking assignments (=) even in
a block with non-blocking assignments (<=).
If nil, all blocking assigned signals are ignored when any
non-blocking assignment is in the AUTORESET block. This allows
blocking assignments to be used for temporary values and not have
those temporaries reset. See example in `verilog-auto-reset'."
:version "24.1"
:version "24.1" ;; rev718
:type 'boolean
:group 'verilog-mode-auto)
(put 'verilog-auto-reset-blocking-in-non 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-reset-widths t
"If true, AUTORESET should determine the width of signals.
"True means AUTORESET should determine the width of signals.
This is then used to set the width of the zero (32'h0 for example). This
is required by some lint tools that aren't smart enough to ignore widths of
the constant zero. This may result in ugly code when parameters determine
the MSB or LSB of a signal inside an AUTORESET."
the constant zero. This may result in ugly code when parameters determine
the MSB or LSB of a signal inside an AUTORESET.
If nil, AUTORESET uses \"0\" as the constant.
If 'unbased', AUTORESET used the unbased unsized literal \"'0\"
as the constant. This setting is strongly recommended for
SystemVerilog designs."
:type 'boolean
:group 'verilog-mode-auto)
(put 'verilog-auto-reset-widths 'safe-local-variable 'verilog-booleanp)
(put 'verilog-auto-reset-widths 'safe-local-variable
'(lambda (x) (memq x '(nil t unbased))))
(defcustom verilog-assignment-delay ""
"Text used for delays in delayed assignments. Add a trailing space if set."
......@@ -1011,7 +1023,7 @@ the MSB or LSB of a signal inside an AUTORESET."
(put 'verilog-assignment-delay 'safe-local-variable 'stringp)
(defcustom verilog-auto-arg-sort nil
"If set, AUTOARG signal names will be sorted, not in declaration order.
"Non-nil means AUTOARG signal names will be sorted, not in declaration order.
Declaration order is advantageous with order based instantiations
and is the default for backward compatibility. Sorted order
reduces changes when declarations are moved around in a file, and
......@@ -1023,7 +1035,7 @@ See also `verilog-auto-inst-sort'."
(put 'verilog-auto-arg-sort 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-inst-dot-name nil
"If true, when creating ports with AUTOINST, use .name syntax.
"Non-nil means when creating ports with AUTOINST, use .name syntax.
This will use \".port\" instead of \".port(port)\" when possible.
This is only legal in SystemVerilog files, and will confuse older
simulators. Setting `verilog-auto-inst-vector' to nil may also
......@@ -1033,7 +1045,7 @@ be desirable to increase how often .name will be used."
(put 'verilog-auto-inst-dot-name 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-inst-param-value nil
"If set, AUTOINST will replace parameters with the parameter value.
"Non-nil means AUTOINST will replace parameters with the parameter value.
If nil, leave parameters as symbolic names.
Parameters must be in Verilog 2001 format #(...), and if a parameter is not
......@@ -1041,7 +1053,7 @@ listed as such there (as when the default value is acceptable), it will not
be replaced, and will remain symbolic.
For example, imagine a submodule uses parameters to declare the size of its
inputs. This is then used by a upper module:
inputs. This is then used by an upper module:
module InstModule (o,i);
parameter WIDTH;
......@@ -1070,20 +1082,20 @@ instead expand to:
(put 'verilog-auto-inst-param-value 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-inst-sort nil
"If set, AUTOINST signal names will be sorted, not in declaration order.
"Non-nil means AUTOINST signals will be sorted, not in declaration order.
Also affects AUTOINSTPARAM. Declaration order is the default for
backward compatibility, and as some teams prefer signals that are
declared together to remain together. Sorted order reduces
changes when declarations are moved around in a file.
See also `verilog-auto-arg-sort'."
:version "24.1"
:version "24.1" ;; rev688
:group 'verilog-mode-auto
:type 'boolean)
(put 'verilog-auto-inst-sort 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-inst-vector t
"If true, when creating default ports with AUTOINST, use bus subscripts.
"Non-nil means when creating default ports with AUTOINST, use bus subscripts.
If nil, skip the subscript when it matches the entire bus as declared in
the module (AUTOWIRE signals always are subscripted, you must manually
declare the wire to have the subscripts removed.) Setting this to nil may
......@@ -1115,6 +1127,12 @@ won't merge conflict."
:type 'integer)
(put 'verilog-auto-inst-column 'safe-local-variable 'integerp)
(defcustom verilog-auto-inst-interfaced-ports t
"Non-nil means include interfaced ports in AUTOINST expansions."
:group 'verilog-mode-auto
:type 'boolean)
(put 'verilog-auto-inst-interfaced-ports 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-input-ignore-regexp nil
"If set, when creating AUTOINPUT list, ignore signals matching this regexp.
See the \\[verilog-faq] for examples on using this."
......@@ -1136,11 +1154,18 @@ See the \\[verilog-faq] for examples on using this."
:type 'string)
(put 'verilog-auto-output-ignore-regexp 'safe-local-variable 'stringp)
(defcustom verilog-auto-template-warn-unused nil
"Non-nil means report warning if an AUTO_TEMPLATE line is not used.
This feature is not supported before Emacs 21.1 or XEmacs 21.4."
:group 'verilog-mode-auto
:type 'boolean)
(put 'verilog-auto-template-warn-unused 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-tieoff-declaration "wire"
"Data type used for the declaration for AUTOTIEOFF. If \"wire\" then
create a wire, if \"assign\" create an assignment, else the data type for
variable creation."
:version "24.1"
"Data type used for the declaration for AUTOTIEOFF.
If \"wire\" then create a wire, if \"assign\" create an
assignment, else the data type for variable creation."
:version "24.1" ;; rev713
:group 'verilog-mode-auto
:type 'string)
(put 'verilog-auto-tieoff-declaration 'safe-local-variable 'stringp)
......@@ -1201,6 +1226,16 @@ For example, \"_t$\" matches typedefs named with _t, as in the C language."
:group 'verilog-mode-auto
:type 'hook)
(defcustom verilog-before-save-font-hook nil
"Hook run before `verilog-save-font-mods' removes highlighting."
:group 'verilog-mode-auto
:type 'hook)
(defcustom verilog-after-save-font-hook nil
"Hook run after `verilog-save-font-mods' restores highlighting."
:group 'verilog-mode-auto
:type 'hook)
(defvar verilog-imenu-generic-expression
'((nil "^\\s-*\\(\\(m\\(odule\\|acromodule\\)\\)\\|primitive\\)\\s-+\\([a-zA-Z0-9_.:]+\\)" 4)
("*Vars*" "^\\s-*\\(reg\\|wire\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3))
......@@ -1430,6 +1465,8 @@ If set will become buffer local.")
:help "Help on AUTOSENSE - sensitivity lists for always blocks"]
["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff)
:help "Help on AUTOTIEOFF - tying off unused outputs"]
["AUTOUNDEF" (describe-function 'verilog-auto-undef)
:help "Help on AUTOUNDEF - undefine all local defines"]
["AUTOUNUSED" (describe-function 'verilog-auto-unused)
:help "Help on AUTOUNUSED - terminating unused inputs"]
["AUTOWIRE" (describe-function 'verilog-auto-wire)
......@@ -1552,7 +1589,7 @@ If set will become buffer local.")
FIXEDCASE and LITERAL as in `replace-match`. STRING is what to replace.
The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\")
will break, as the o's continuously replace. xa -> x works ok though."
;; Hopefully soon to a emacs built-in
;; Hopefully soon to an Emacs built-in
;; Also note \ in the replacement prevent multiple replacements; IE
;; (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil "wire@_@")
;; Gives "wire\([0-9]+\)_@" not "wire\([0-9]+\)_\([0-9]+\)"
......@@ -2401,7 +2438,6 @@ find the errors."
"\\|\\(\\<`[ou]vm_[a-z_]+_begin\\>\\)" ;28
"\\|\\(\\<`vmm_[a-z_]+_member_begin\\>\\)"
;;
))
(defconst verilog-end-block-ordered-rry
......@@ -2629,11 +2665,11 @@ find the errors."
"endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
))))
(defconst verilog-disable-fork-re "\\(disable\\|wait\\)\\s-+fork\\>")
(defconst verilog-extended-case-re "\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?")
(defconst verilog-extended-case-re "\\(\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
(defconst verilog-extended-complete-re
(concat "\\(\\<extern\\s-+\\|\\<\\(\\<pure\\>\\s-+\\)?virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)"
"\\|\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)"
"\\|\\(\\<import\\>\\s-+\\)?\"DPI-C\"\\s-+\\(function\\>\\|task\\>\\)"
(concat "\\(\\(\\<extern\\s-+\\|\\<\\(\\<pure\\>\\s-+\\)?virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)\\)"
"\\|\\(\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)\\)"
"\\|\\(\\(\\<import\\>\\s-+\\)?\\(\"DPI-C\"\\s-+\\)?\\(\\<pure\\>\\s-+\\)?\\(function\\>\\|task\\>\\)\\)"
"\\|" verilog-extended-case-re ))
(defconst verilog-basic-complete-re
(eval-when-compile
......@@ -2645,9 +2681,7 @@ find the errors."
))))
(defconst verilog-complete-reg
(concat
verilog-extended-complete-re
"\\|"
verilog-basic-complete-re))
verilog-extended-complete-re "\\|\\(" verilog-basic-complete-re "\\)"))
(defconst verilog-end-statement-re
(concat "\\(" verilog-beg-block-re "\\)\\|\\("
......@@ -2764,7 +2798,8 @@ See also `verilog-font-lock-extra-types'.")
(defvar verilog-font-lock-keywords-3 nil
"Gaudy level highlighting for Verilog mode.
See also `verilog-font-lock-extra-types'.")
(defvar verilog-font-lock-translate-off-face
(defvar verilog-font-lock-translate-off-face
'verilog-font-lock-translate-off-face
"Font to use for translated off regions.")
(defface verilog-font-lock-translate-off-face
......@@ -2842,8 +2877,8 @@ See also `verilog-font-lock-extra-types'.")
(verilog-pragma-keywords
(eval-when-compile
(verilog-regexp-opt
'("surefire" "synopsys" "rtl_synthesis" "verilint" "leda" "0in") nil
)))
'("surefire" "auto" "synopsys" "rtl_synthesis" "verilint" "leda" "0in"
) nil )))
(verilog-1800-2005-keywords
(eval-when-compile
......@@ -2968,7 +3003,7 @@ See also `verilog-font-lock-extra-types'.")
(append verilog-font-lock-keywords-1
(list
;; Fontify pragmas
(concat "\\(//\\s-*" verilog-pragma-keywords "\\s-.*\\)")
(concat "\\(//\\s-*\\(" verilog-pragma-keywords "\\)\\s-.*\\)")
;; Fontify escaped names
'("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face)
;; Fontify macro definitions/ uses
......@@ -3030,6 +3065,31 @@ For insignificant changes, see instead `verilog-save-buffer-state'."
after-change-functions)
(progn ,@body)))
(defvar verilog-save-font-mod-hooked nil
"Local variable when inside a `verilog-save-font-mods' block.")
(make-variable-buffer-local 'verilog-save-font-mod-hooked)
(defmacro verilog-save-font-mods (&rest body)
"Execute BODY forms, disabling text modifications to allow performing BODY.
Includes temporary disabling of `font-lock' to restore the buffer
to full text form for parsing. Additional actions may be specified with
`verilog-before-save-font-hook' and `verilog-after-save-font-hook'."
;; Before version 20, match-string with font-lock returns a
;; vector that is not equal to the string. IE if on "input"
;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
`(let* ((hooked (unless verilog-save-font-mod-hooked
(verilog-run-hooks 'verilog-before-save-font-hook)
t))
(verilog-save-font-mod-hooked t)
(fontlocked (when (and (boundp 'font-lock-mode) font-lock-mode)
(font-lock-mode 0)
t)))
(unwind-protect
(progn ,@body)
;; Unwind forms
(when fontlocked (font-lock-mode t))
(when hooked (verilog-run-hooks 'verilog-after-save-font-hook)))))
;;
;; Comment detection and caching
......@@ -3161,7 +3221,7 @@ to establish comment properties on all text."
(defun verilog-insert (&rest stuff)
"Insert STUFF arguments, tracking for `verilog-inside-comment-or-string-p'.
Any insert that includes a comment must have the entire commente
Any insert that includes a comment must have the entire comment
inserted using a single call to `verilog-insert'."
(let ((pt (point)))
(while stuff
......@@ -3565,9 +3625,10 @@ Key bindings specific to `verilog-mode-map' are:
;; Stuff for GNU Emacs
(set (make-local-variable 'font-lock-defaults)
`((verilog-font-lock-keywords verilog-font-lock-keywords-1
verilog-font-lock-keywords-2
verilog-font-lock-keywords-3)
`((verilog-font-lock-keywords
verilog-font-lock-keywords-1
verilog-font-lock-keywords-2
verilog-font-lock-keywords-3)
nil nil nil
,(if (functionp 'syntax-ppss)
;; verilog-beg-of-defun uses syntax-ppss, and syntax-ppss uses
......@@ -4049,7 +4110,7 @@ With ARG, first kill any existing labels."
(if (looking-at verilog-label-re)
(setq h (point))))
(goto-char h)))
;; stop if we see a complete reg, perhaps an extended one
;; stop if we see an extended complete reg, perhaps a complete one
(and
(looking-at verilog-complete-reg)
(let* ((p (point)))
......@@ -4186,32 +4247,20 @@ More specifically, point @ in the line foo : @ begin"
nil)))
(defun verilog-backward-up-list (arg)
"Like `backward-up-list', but deal with comments."
"Call `backward-up-list' ARG, ignoring comments."
(let ((parse-sexp-ignore-comments t))
(backward-up-list arg)))
(defun verilog-forward-sexp-cmt (arg)
"Call `forward-sexp', inside comments."
"Call `forward-sexp' ARG, inside comments."
(let ((parse-sexp-ignore-comments nil))
(forward-sexp arg)))
(defun verilog-forward-sexp-ign-cmt (arg)
"Call `forward-sexp', ignoring comments."
"Call `forward-sexp' ARG, ignoring comments."
(let ((parse-sexp-ignore-comments t))
(forward-sexp arg)))
(defun verilog-in-struct-region-p ()
"Return true if in a struct region.
More specifically, in a list after a struct|union keyword."
(interactive)
(save-excursion
(let* ((state (verilog-syntax-ppss))
(depth (nth 0 state)))
(if depth
(progn (verilog-backward-up-list depth)
(verilog-beg-of-statement)
(looking-at "\\<typedef\\>?\\s-*\\<struct\\|union\\>"))))))
(defun verilog-in-generate-region-p ()
"Return true if in a generate region.
More specifically, after a generate and before an endgenerate."
......@@ -4658,10 +4707,10 @@ primitive or interface named NAME."
(cond
((match-end 5) ;; of verilog-end-block-ordered-re
(setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
(setq name-re "\\w+\\s-*(")
)
(setq name-re "\\w+\\s-*("))
((match-end 6) ;; of verilog-end-block-ordered-re
(setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)"))
(setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
(setq name-re "\\w+\\s-*("))
((match-end 7) ;; of verilog-end-block-ordered-re
(setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
((match-end 8) ;; of verilog-end-block-ordered-re
......@@ -4977,25 +5026,24 @@ becomes:
(compile compile-command))
(defun verilog-preprocess (&optional command filename)
"Preprocess the buffer, similar to `compile', but leave output in Verilog-Mode.
"Preprocess the buffer, similar to `compile', but put output in Verilog-Mode.
Takes optional COMMAND or defaults to `verilog-preprocessor', and
FILENAME or defaults to `buffer-file-name`."
FILENAME to find directory to run in, or defaults to `buffer-file-name`."
(interactive
(list
(let ((default (verilog-expand-command verilog-preprocessor)))
(set (make-local-variable `verilog-preprocessor)
(read-from-minibuffer "Run Preprocessor (like this): "
default nil nil
'verilog-preprocess-history default)))))
(read-from-minibuffer "Run Preprocessor (like this): "
default nil nil
'verilog-preprocess-history default)))))
(unless command (setq command (verilog-expand-command verilog-preprocessor)))
(let* ((fontlocked (and (boundp 'font-lock-mode) font-lock-mode))
(dir (file-name-directory (or filename buffer-file-name)))
(file (file-name-nondirectory (or filename buffer-file-name)))
(cmd (concat "cd " dir "; " command " " file)))
(dir (file-name-directory (or filename buffer-file-name)))
(cmd (concat "cd " dir "; " command)))
(with-output-to-temp-buffer "*Verilog-Preprocessed*"
(with-current-buffer (get-buffer "*Verilog-Preprocessed*")
(insert (concat "// " cmd "\n"))
(shell-command cmd "*Verilog-Preprocessed*")
(call-process shell-file-name nil t nil shell-command-switch cmd)
(verilog-mode)
;; Without this force, it takes a few idle seconds
;; to get the color, which is very jarring
......@@ -5006,17 +5054,30 @@ FILENAME or defaults to `buffer-file-name`."
;; Batch
;;
(defun verilog-warn (string &rest args)
"Print a warning with `format' using STRING and optional ARGS."
(apply 'message (concat "%%Warning: " string) args))
(defun verilog-warn-error (string &rest args)
"Call `error' using STRING and optional ARGS.
If `verilog-warn-fatal' is non-nil, call `verilog-warn' instead."
(if verilog-warn-fatal
(apply 'error string args)
(apply 'verilog-warn string args)))
(defmacro verilog-batch-error-wrapper (&rest body)
"Execute BODY and add error prefix to any errors found.
This lets programs calling batch mode to easily extract error messages."
`(condition-case err
(progn ,@body)