Commit 6dfe231c authored by Mattias Engdegård's avatar Mattias Engdegård
Browse files

Rename variable for clarity

* lisp/progmodes/verilog-mode.el (verilog-sk-define-signal):
Rename sig-re to sig-chars, to make it clear that it isn't a regexp.
parent a35e06bb
Pipeline #1194 failed with stage
in 60 minutes and 2 seconds
......@@ -14263,13 +14263,13 @@ and the case items."
(defun verilog-sk-define-signal ()
"Insert a definition of signal under point at top of module."
(interactive "*")
(let* ((sig-re "a-zA-Z0-9_")
(let* ((sig-chars "a-zA-Z0-9_")
(v1 (buffer-substring
(skip-chars-backward sig-re)
(skip-chars-backward sig-chars)
(skip-chars-forward sig-re)
(skip-chars-forward sig-chars)
(if (not (member v1 verilog-keywords))
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