Commit e25e7d81 authored by Wilson Snyder's avatar Wilson Snyder

Fix verilog-mode vmm statements and AUTOINPUTREG ignores.

* lisp/progmodes/verilog-mode.el (verilog-vmm-statement-re):
Fix vmm statement regexps. Reported by Mattias Engdegard.
(verilog-auto-reg-input)
(verilog-auto-reg-input-assigned-ignore-regexp): For AUTOINPUTREG,
allow ignoring assignments with new
`verilog-auto-reg-input-assigned-ignore-regexp' variable, bug1401.
Reported by David Rogoff.
parent f9ff60e0
Pipeline #1140 failed with stage
in 40 minutes and 12 seconds
......@@ -121,7 +121,7 @@
;;
;; This variable will always hold the version number of the mode
(defconst verilog-mode-version "2019-03-05-39b4dac-vpo-GNU"
(defconst verilog-mode-version "2019-04-02-5d62d3f-vpo-GNU"
"Version of this Verilog mode.")
(defconst verilog-mode-release-emacs t
"If non-nil, this version of Verilog mode was released with Emacs itself.")
......@@ -1285,6 +1285,13 @@ See the \\[verilog-faq] for examples on using this."
:type '(choice (const nil) regexp))
(put 'verilog-auto-input-ignore-regexp 'safe-local-variable 'stringp)
(defcustom verilog-auto-reg-input-assigned-ignore-regexp nil
"If non-nil, when creating AUTOINPUTREG, ignore signals matching this regexp."
:version "27.1"
:group 'verilog-mode-auto
:type '(choice (const nil) regexp))
(put 'verilog-auto-reg-input-assigned-ignore-regexp 'safe-local-variable 'stringp)
(defcustom verilog-auto-inout-ignore-regexp nil
"If non-nil, when creating AUTOINOUT, ignore signals matching this regexp.
See the \\[verilog-faq] for examples on using this."
......@@ -2144,14 +2151,7 @@ find the errors."
) nil ) ) )
(defconst verilog-vmm-statement-re
(eval-when-compile
(verilog-regexp-opt
'(
"`vmm_\\(data\\|env\\|scenario\\|subenv\\|xactor\\)_member_\\(scalar\\|string\\|enum\\|vmm_data\\|channel\\|xactor\\|subenv\\|user_defined\\)\\(_array\\)?"
;; "`vmm_xactor_member_enum_array"
;; "`vmm_xactor_member_scalar_array"
;; "`vmm_xactor_member_scalar"
) nil )))
"`vmm_\\(data\\|env\\|scenario\\|subenv\\|xactor\\)_member_\\(scalar\\|string\\|enum\\|vmm_data\\|channel\\|xactor\\|subenv\\|user_defined\\)\\(_array\\)?")
(defconst verilog-ovm-statement-re
(eval-when-compile
......@@ -2973,7 +2973,8 @@ find the errors."
;; `timescale time_unit / time_precision
"\\<\\(`timescale\\)\\>\\s-+10\\{0,2\\}\\s-*[munpf]?s\\s-*/\\s-*10\\{0,2\\}\\s-*[munpf]?s"
"\\)\\|\\(?:"
;; `define and `if can span multiple lines if line ends in '\'. NOTE: `if is not IEEE 1800-2012
;; `define and `if can span multiple lines if line ends in '\'.
;; NOTE: `if is not IEEE 1800-2012.
;; from http://www.emacswiki.org/emacs/MultilineRegexp
(concat "\\<\\(`define\\|`if\\)\\>" ; directive
"\\s-+" ; separator
......@@ -12078,15 +12079,18 @@ Typing \\[verilog-auto] will make this into:
(defun verilog-auto-reg-input ()
"Expand AUTOREGINPUT statements, as part of \\[verilog-auto].
Make reg statements instantiation inputs that aren't already declared.
This is useful for making a top level shell for testing the module that is
to be instantiated.
Make reg statements instantiation inputs that aren't already
declared or assigned to. This is useful for making a top level
shell for testing the module that is to be instantiated.
Limitations:
This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').
This does NOT work on memories, declare those yourself.
Assignments cause the assigned-to variable not to be declared unless
the name matches `verilog-auto-reg-input-assigned-ignore-regexp'.
An example (see `verilog-auto-inst' for what else is going on here):
module ExampRegInput (o,i);
......@@ -12124,7 +12128,9 @@ Typing \\[verilog-auto] will make this into:
(append (verilog-subdecls-get-inputs modsubdecls)
(verilog-subdecls-get-inouts modsubdecls))
(append (verilog-decls-get-signals moddecls)
(verilog-decls-get-assigns moddecls))))))
(verilog-signals-not-matching-regexp
(verilog-decls-get-assigns moddecls)
verilog-auto-reg-input-assigned-ignore-regexp))))))
(when sig-list
(verilog-forward-or-insert-line)
(verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n")
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment